From Critical Paths to Critical Cells: Learning Fine-Grained Timing Attribution for Chip Design

Identifying which components of a system to improve is difficult when supervision is available only for aggregated outcomes. Timing optimization in chip design presents this challenge: static timing analysis (STA) identifies timing-critical paths, while placement refinement is made on cells whose contributions to a path's timing degradation may differ. Identifying a critical path does not by itself reveal the cells whose optimization would most improve timing. We study **timing-critical cell identification**, the task of learning cell-level timing guidance from path-level observations without cell-level annotations. We introduce CritiCell, a multiple instance learning framework that represents timing paths as bags of cells and learns cell scores from their aggregate timing behavior. We also utilize these scores to guide both constraint-driven and objective-driven placement in the ICCAD2015 benchmark suite. Compared with coarse path-level guidance, our fine-grained CritiCell improves worst negative slack (WNS) and total negative slack (TNS) by 2.87% and 10.74% in constraint-driven placement, and by 4.08% and 10.56% in objective-driven placement. These results show that coarse supervision can produce fine-grained guidance useful for downstream optimization tasks.