TP3D: Timing-Aware Die-To-Die 3D Macro Placement

Macro placement is one of the most critical steps in chip design, exerting a significant impact on power, performance, and area (PPA), while existing works primarily focus on optimizing computationally efficient surrogate objectives, resulting in a marked gap in performance improvement. The emergence of 3D integrated circuits (3D-ICs) with stacked layers connected via hybrid bonding terminals (HBTs) further complicates accurate timing estimation at early stages of the design flow. To bridge the gap, we formulate the timing-aware macro placement in 3D-ICs design as a learning-based optimization problem, and propose TP3D, a novel learning-based, timing-aware 3D macro placement framework. Specifically, TP3D introduces a structured timing prediction model that decomposes intra-die interactions and bridge-point-based inter-die interactions. The predicted metrics are further integrated into the placement procedure in the form of timing masks to guide optimization. Extensive experiments demonstrate that TP3D outperforms state-of-the-art methods, achieving an average improvement of 10.8% in Worst Negative Slack (WNS) and 8.7% in Total Negative Slack (TNS), which are of great significance for enhancing chip performance. Notably, this work highlights the importance of integrating structured, learnable objective modeling for intractable objectives, compared to directly optimizing surrogate objectives.