EAPlace-VLM: Evolutionary Macro Placement via Vision-Language Topological Diagnosis and Grid-Free Continuous Refinement

Macro placement is a fundamental yet highly challenging problem in modern chip design, characterized by large-scale combinatorial complexity, high-dimensional constraints, and strong sensitivity to early decisions. Existing methods, including analytical optimization, reinforcement learning, and heuristic-based approaches, have achieved notable progress but still suffer from inherent limitations such as difficulty in handling discrete constraints, sample inefficiency, and susceptibility to local optima caused by sequential decision-making. In particular, heuristic-driven relocation strategies often exhibit limited global awareness, leading to suboptimal solutions. To address these challenges, this paper proposes EAPlace-VLM, a novel dual-engine evolutionary framework that integrates vision-language models (VLMs) into macro placement. The proposed method extends traditional heuristic optimization into a unified paradigm combining multimodal semantic reasoning and continuous physical refinement. Specifically, a VLM is incorporated as a low-frequency topological diagnostician within the evolutionary loop to guide macro relocation decisions, thereby alleviating the spatial myopia of conventional heuristics. To enable effective cross-modal reasoning, we introduce a topology-to-color visual encoding scheme that transforms hypergraph connectivity into perceptually meaningful patterns, allowing the VLM to perform zero-shot spatial analysis and identify problematic macro clusters. Furthermore, a grid-free continuous physical refinement module is developed to eliminate discretization artifacts via legality-aware sub-pixel optimization in continuous space, improving layout compactness and physical fidelity. Experimental results on the standard ISPD 2005 benchmarks demonstrate that EAPlace-VLM achieves the state-of-the-art performance. Compared to the leading baseline EGPlace, our framework significantly reduces wirelength by up to 25% while maintaining a negligible refinement computational overhead of less than 2.5%, securing the best average rank in both pure macro and mixed-size global placement tasks.