Generative Latent Optimization for 3D Floorplanning

Floorplanning determines the positions and shapes of circuit blocks within a chip outline while minimizing interconnect length and satisfying geometric constraints such as non-overlap and boundary containment. 3D floorplanning extends this problem by adding cross-die block alignment, making the feasible layout space highly coupled and difficult to optimize. Existing approaches often use Reinforcement Learning for floorplanning problems which can require careful hyperparameter tuning and long training time. We instead introduce Latent Geometric Optimization (LGO), which learns a structured latent representation of complete floorplans and searches this representation after training. A Transformer VAE encodes block geometry and layout variables, an evolutionary optimizer searches the latent space, and the decoder maps the latent codes back to the geometric domain. Searching this learned layout manifold enables coordinated global changes within and across dies. On MCNC and GSRC 3D floorplanning benchmarks, our approach outperforms the best-performing baseline on 7 of the 8 tested benchmark instances, with a mean improvement of 7.5%, despite being trained on a relatively weak dataset. We further demonstrate that our model is able to effectively generalize to unseen circuits with unseen block counts. Results suggest that LGO's relative advantage grows as the number of relational constraints between objects increases.