MUL-GPT: Timing-Structure-Aware Generative Optimization for Multiplier Circuits

Multiplier optimization is a challenging combinatorial optimization problem, as its design space grows rapidly with increasing operand bit width. In recent years, learning-driven methods have provided a promising approach to discovering high-speed and area-efficient circuit structures. However, existing methods typically optimize only a small set of global post-synthesis metrics, such as area and delay, without explicitly modeling the internal timing structure of multipliers or the mechanisms underlying critical path formation. Consequently, they struggle to accurately identify timing bottlenecks and effectively exploit internal timing information to guide structural optimization. To address these limitations, we propose MUL-GPT, an internal-timing-structure-aware generative framework for multiplier optimization. MUL-GPT is a generative pretrained Transformer (GPT)-style generative framework that addresses the internally coupled timing optimization problem of multipliers. It unifies constrained autoregressive compressor-tree generation, arrival-time-conditioned adder optimization, and static timing analysis (STA)-guided local interconnection rewiring, with internal timing information serving as the link across these stages. Experiments show that the best designs found by MUL-GPT consistently outperform state-of-the-art methods across various arithmetic-unit design tasks, reducing the area-delay product (ADP) by up to 10.57%. These improvements are preserved when the optimized arithmetic units are integrated into large-scale artificial-intelligence (AI)-accelerator circuits, where MUL-GPT achieves an ADP reduction of up to 7.90%, further demonstrating its scalability and practical applicability.