HierRTL: Hierarchical Graph Representation Learning for Multi-Granularity RTL Performance Modeling

Accurate power, performance, and area (PPA) assessment requires time-consuming synthesis and physical-design flows, limiting design-space exploration at the register-transfer level (RTL). Fast RTL prediction must capture both fine-grained hardware structure and design-wide context while preserving the association between logic and the state updates it supports. We propose HierRTL, a hierarchical Graph U-Net for joint design-level PPA and register-level timing prediction. HierRTL organizes RTL graphs into overlapping register cones that capture the data and control dependencies of individual next-state updates, with a directed cone graph modeling dependencies between registers. A U-shaped encoder–decoder aggregates information from nodes to cones and the design, then routes context back to nodes through the same cone memberships. This bidirectional hierarchy preserves shared-logic associations and produces contextualized node representations for predicting design-level area, power, worst negative slack, and total negative slack, together with register-level setup slack. To support local RTL optimization, we construct bounded local rewrites, verify them against the original RTL, and evaluate accepted implementations with a common flow. These equivalence-verified results define a soft opportunity target for each editable region. Starting from the jointly supervised predictor, HierRTL encodes the unmodified design once, summarizes each region only at readout, and learns four listwise rankings over the regions of the same design. Candidate implementations define supervision but are not required as model inputs. This connects multi-granularity RTL performance modeling with the practical task of prioritizing regions that are more likely to yield high optimization value before expensive search.