ECOpilot: A Circuit-Aware Multimodal LLM Representation Learning Framework for Timing Reasoning and Optimization

Digital-circuit timing depends on connectivity, cell behavior, and operating conditions, which are difficult to capture through text alone. We introduce ECOpilot, a multimodal representation learning framework that makes these complementary signals available to a pretrained large language model (LLM). A graph encoder and projection align circuit structure with a frozen language backbone through self-supervised masked gate modeling and tool-supervised arrival-time regression. A cell representation combines learned delay-surface features with logical effort, an analytical descriptor of cell driving behavior. Together with textual operating conditions, these representations support timing prediction and tool-guided optimization of cell replacements. On held-out circuits implemented in a TSMC 7 nm technology, ECOpilot achieves 8.6% mean absolute percentage error in arrival-time prediction. Downstream timing engineering change order (ECO) reduces worst-negative-slack magnitude by up to 85.9% and violating-path count by up to 96.0%, measured from per-corner averages across three test designs. Prediction, feature-ablation, and optimization results support combining explicit circuit structure with physical and logical cell knowledge.