CellBench: Benchmarking Generalization in Fast Standard Cell Evaluation

Standard cell libraries are collections of reusable building blocks for very large scale integration (VLSI) circuits. Developing and optimizing cell libraries involves exploring a large design space of pre-layout netlists with diverse size configurations, topologies, and functions. For each candidate netlist, accurate evaluation of power, performance, and area (PPA) requires time-consuming layout generation and simulation, creating a bottleneck in design exploration. Machine learning can alleviate this bottleneck through fast prediction, but generalization to unseen cell designs remains insufficiently evaluated. To address this evaluation gap, we introduce CellBench, the first open dataset and benchmark for fast standard cell evaluation, covering PPA and constrained routability prediction and evaluating generalization to unseen size configurations, topologies, and functions. Building upon the ASAP7 7 nm FinFET process design kit, we generate diverse pre-layout netlists through cell library extension, topology generation, and transistor size assignment, yielding 118,906 netlists for PPA prediction and 296,274 for constrained routability prediction. Evaluation of existing prediction methods shows declining overall performance from unseen size configurations to unseen topologies and functions. Further analysis shows that structural similarity to training circuits helps explain PPA prediction errors, whereas functional similarity alone does not consistently reflect prediction difficulty. The benchmark is available for anonymous review.