Can Ground-Capacitance Predictors Generalize Across Circuit Domains?

Producing circuit layouts requires substantial engineering effort, and failed post- layout verification can trigger further layout, extraction, and simulation iterations. These costs, together with restricted access to circuit intellectual property, make labeled parasitic data scarce when entering a new circuit regime. Learning-based prediction could provide earlier electrical feedback, but its usefulness in this cold-start setting depends on reusing data from other circuit domains. We study target-label-free, node-level ground-capacitance prediction across Digital, Analog, and SRAM circuits, where similar graph structures can carry different physical contexts and loading behavior. We propose XRC-Former, a graph Transformer that preserves circuit context through domain-sensitive encoding, reuses structural prototypes through shared memory, and aligns only a designated invariant branch while retaining a non-aligned residual for prediction. Under leave-one-domain- out evaluation, using source labels for training and source validation for model selection, XRC-Former achieves the best target-domain R2 among 14 task-adapted baselines. It remains positive in the difficult Analog-target setting, where most baselines obtain negative R2. Ablations, embedding diagnostics, and supervised within-domain references characterize the roles and scope of the proposed transfer mechanism. The results support cross-domain GC prediction as a step toward reusable parasitic screening before the final layout stage, rather than a replacement for signoff verification.