Chip Capacitance Prediction by a Jointly Routed Transformer

Accurate parasitic capacitance estimation is essential for chip design and verification. Lookup-table-based parasitic extraction (LUT-based PEX) reuses precomputed capacitance tables to avoid weeks to months of physical simulations, but sparse coverage limits accuracy for unobserved chip layout geometries. To address this limitation, we propose a jointly routed Transformer for chip capacitance prediction, conditioned on layout geometry, material context, and available capacitance observations. Our key idea is to train a shared Transformer to jointly learn residual corrections to an interpolation estimate and adaptive weights for combining neural and numerical corrections. Notably, the model extrapolates beyond the observed geometry range and enables transfer to an unseen manufacturing process without parameter updates, aided by our structured tokenizer. Moreover, we curate and augment a unified dataset and evaluation suite for capacitance prediction from sparse observations, advancing AI research in LUT-based PEX. Our method outperforms commercial-style multilinear interpolation in all 15 evaluated settings and reduces normalized extrapolation error by 84–86% on public tables. Encouragingly, these gains extend to downstream chip analysis: timing estimates using our predicted capacitances more closely match the full-table reference in all 16 settings across eight fixed layouts.