BiG-Flow: Program-Conditioned Discrete Flow Matching for High-Level Synthesis Pragma Design

High-level synthesis (HLS) allows software developers to build FPGA accelerators from C/C++ kernels, but the quality of the resulting hardware depends on the inserted pragmas that take hardware expertise to choose, and every candidate design needs minutes to hours of synthesis. Learned HLS tools predict the quality of results (QoR) of a design and then search the design space of each new kernel with that predictor, which costs many predictions and synthesis runs per kernel and generalizes poorly to kernels outside the training set. We present BiG-Flow, a bidirectional graph flow-matching model conditioned on the program. One network generates pragma designs for a requested QoR and predicts the QoR of a given design, directly and without per-kernel search or fine-tuning. BiG-Flow encodes the control and data flow graph of a kernel once as context, generates designs with a discrete flow over the pragma sites of the kernel, predicts QoR with a continuous flow, and keeps every generated pragma within its legal values. We evaluate on an expanded HLSyn benchmark and 22 test kernels that are never seen in the training stage, with Vitis HLS as the oracle. BiG-Flow predicts latency with at least 17% lower error than state-of-the-art graph predictors. Given the QoR of a held-out design as the request, it returns a valid design within a factor of two of the requested latency for 58% of requests, against 41% for unconditional sampling. Asked for $10\times$ to $1000\times$ speedups with 20 synthesis runs per kernel, it reaches a geometric-mean speedup of $8.6\times$ over the unoptimized design and up to $445\times$ on a single kernel, which is $1.7\times$ the speedup of random legal designs, $1.6\times$ that of the strongest LLM-based baseline, and $1.5\times$ that of AutoDSE given the same synthesis time. On one kernel it finds a design $13.4\times$ faster than the best design of a full AutoDSE search.