H-OSIRIS: Hierarchical Layout-Aware Analog Circuit Sizing and Footprint Optimization using Deep Reinforcement Learning

The automation of analog integrated-circuit layout remains challenging because circuit performance depends on coupled interaction among device sizing, parasitics, layout-dependent effects, and physical area. These effects are difficult to model accurately with rule-based or template-driven methods, particularly as circuits grow from individual functional blocks into multi-block systems. While machine learning has shown promising results for isolated stages of the analog design flow, an automated back-end optimization methodology that exploits the multi-block hierarchy of a layout while leveraging parasitic-aware feedback remains largely unexplored. This paper presents H-OSIRIS, a deep reinforcement learning methodology for post-layout optimization of multi-block analog circuits. H-OSIRIS operates at two optimization levels *(i)* it allocates area across circuit blocks globally and *(ii)* performs local ε-sizing of block devices. Guided by post-layout feedback, these mechanisms align post-layout functional metrics with their pre-layout references while reducing the overall layout footprint. Across four analog topologies and six metric sets, H-OSIRIS achieves 87% joint feasibility on held-out test samples while reducing the median layout area by 5.5%.