AnaFlash: AI-driven Sizing of Analog Circuit using Fast Analytical Circuit Models

Analog circuit sizing requires jointly satisfying coupled performance specifications whose response to device dimensions depends on the circuit topology, operating point, and technology process. Recent AI-based workflows either require substantial circuit-specific training data or ask large language models (LLMs) to directly propose numerical device updates from simulator feedback while the absense of an analytical solver of the equation of the circuit creates trial and error feedback loop approaches. This paper AnaFlash, a hybrid AI-analytical sizing framework in which a fast circuit model, rather than the LLM, drives numerical exploration. Starting from a physically valid seed, AnaFlash derives a SPICE-based quality-metric sensitivity model and computes sizing updates through constrained optimization. SPICE validates each candidate, while a lightweight LLM is invoked only when the analytical engine detects a locally unproductive sizing update. The LLM then revises metric priorities rather than transistor dimensions. Across six OTA topologies and five $GMC$ filter topologies, three technology processes, and thirty specification configurations per circuit–process pair, AnaFlash achieves training-free transfer with $100\%$ OTA success and $94.7-100\%$ filter success. AnaFlash requires only between 17 and 236 SPICE simulations on average for the circuit sizing to converge and achieves up to $56\times$ lower runtime than recent sizing workflows on shared benchmarks.