TRACE: LLM-Orchestrated Bayesian Optimization for Analog Circuit Sizing

An analog circuit sizing task must reconcile competing specifications across testbenches and process, voltage, and temperature corners through costly circuit simulations. Bayesian optimization (BO) reuses these evaluations to guide sampling, but a stalled loss curve alone does not identify the circuit-level cause or the intervention it calls for. We introduce TRACE, an LLM-orchestrated framework that composes the sizing workflow online as simulation evidence accumulates. At each decision point, TRACE refreshes six diagnostic views of the committed results, reads them alongside device roles and circuit topology, and decides whether, when, and at what scope to act: continue BO, refine a local candidate, explore an unsampled region, or revise the sizing task. Each decision stays bound to the evidence available when it was made, so an episode can be replayed and its design checked against simulator records. On four circuits in a TSMC 28 nm process with Cadence Spectre, TRACE returns a fully verified design in every run and achieves the lowest mean simulation count among the compared methods. Relative to TRACE, tSS-BO requires $2.09$–$4.96\times$ as many simulations and $1.62$–$3.96\times$ as much wall time. Action ablations show that neither single intervention is uniformly best across the tested circuits.