CodePaint: Generating IC Layouts in a Learned Discrete Space

Early design-technology co-optimization requires both rule-clean layout patterns that satisfy design rules and rule-targeted patterns with specified critical dimensions. Meeting these requirements is challenging because small geometric variations can violate design rules, while sampling from a pre-trained natural image distribution offers limited controllability. We present CodePaint, a framework for controllable IC layout generation in a learned discrete space. A vector-quantized vocabulary captures local layout features, and absorbing diffusion completes their spatial configurations through one-way token updates that preserve context and revealed tokens. For rule-targeted generation, we introduce TokenProbe, which selects tokens to retain during completion by probing encoder responses to geometric perturbations, without additional training. On ASAP7, CodePaint achieves 75.69% direct DRC compliance compared with 12.00% for PatternPaint, rising to 78.38% after cleanup. For rule-targeted generation, TokenProbe achieves a valid target realization rate of 22.5%,  50% higher than the fixed-block baseline. On a commercial 16 nm PDK, CodePaint adapted with only 20 target clips outperforms PatternPaint adapted with 100 clips. These results establish a strong pretrained layout prior for geometrically faithful generation, local control, and sample-efficient PDK adaptation.