Topological Path Signatures under Physical Micro-Fractures: Pareto-Optimal Battery Degradation Estimation on Edge Microcontrollers

Sequence learning paradigms demonstrate low empirical error on curated laboratory battery benchmarks, yet rely upon an unstated operational prior: continuous, uniformly sampled charging trajectories globally aligned to a standardized temporal axis. In commercial vehicular deployment, this prior is violated by physical micro-fractures, including unanchored opportunistic charging slices ($5\%$-$25\%$ State-of-Charge intervals), sensor quantization floors ($10\text{mV}$ ADC steps), and stochastic communication dropouts. Under this manifold, continuous spline-based ODE solvers encounter numerical stiffness deadlocks, self-attention mechanisms undergo key-padding dilution, and unrolled hidden states exceed edge microcontroller (MCU) memory bounds. In this work, we present RIIS-MicroBurst, an edge-native framework utilizing a parameter-free feature extraction operator formulated in free Lie algebra. By replacing numerical integration with deterministic tensor-vector operations via Chen's identity, RIIS maps arbitrary variable-length inputs into a static, invariant geometric representation. Combined with thermodynamic phase-plane scaling and a closed-form Geometry-Oracle, RIIS establishes a new Pareto efficiency frontier across simulation, dynamic stress, synthetic fault, and commercial fleet benchmarks. Operating strictly within automotive MCU hardware ceilings ($\le 1\text{MB}$ SRAM, $\le 10^5$ FLOPs), it achieves state-of-the-art accuracy while delivering $4,900\times$ to $57,000\times$ lower computational operations compared to recurrent and continuous baselines.