Never Step Back: Monotonic LLM Optimization for Circuit Layout Generation

Recent advances in large language models (LLMs) suggest strong potential for automating analog layout design. Yet existing iterative approaches suffer from non-monotonic refinement, where unsuccessful constraint updates may degrade previously verified layouts and propagate errors across subsequent iterations. Moreover, limited reuse of verified design experience across tasks leads to repeated failures and ineffective design exploration. To address these challenges, we propose **MONA**, a training-free multi-agent framework for monotonic analog layout optimization. MONA integrates Adaptive Layout Search (ALS) with Verification-Aware Memory (VAM) and an open-source EDA flow. ALS explores complementary constraint strategies to enable effective design exploration, while VAM employs a Verification Gate to preserve the best deliverable layout and Long-term Memory to distill verified experience for cross-task transfer, accelerating convergence without compromising previously achieved design quality. Across 6 SKY130 analog layout tasks, MONA achieves a $98.9\%$ deliverable-layout success rate, a $2.02\times$ higher success rate than the strongest evaluated LLM-based method, while attaining the highest mean FoM across all tasks. Moreover, MONA reduces LLM tokens per deliverable layout by $53.2\%$, demonstrating reliable and resource-efficient analog layout optimization.