SAAC: Sizing Agent for Analog Circuit via Turn-Level Reinforcement Learning

Analog circuit sizing (ACS) is a critical yet challenging iterative optimization task in electronic design automation (EDA), requiring domain expertise, multiple expensive simulations, and the balancing of conflicting performance objectives. Existing optimization approaches face distinct limitations: traditional black-box methods like Bayesian Optimization ignore the reasoning process and prior knowledge, relying instead on extensive sampling that scales poorly with design complexity. While large language models (LLMs) offer promising reasoning capabilities, current LLM-based ACS workflows either depend heavily on the base model's inherent abilities or require costly human-annotated data for training, and existing RL-based methods also fail to perform fine-grained, turn-level optimization at each iteration. To address these gaps, we propose SAAC (Sizing Agent for Analog Circuit), an agentic framework specifically tailored for analog circuit sizing. SAAC integrates a professional-grade simulation environment that provides standardized tool interactions and verifiable reward signals, coupled with an automated data synthesis pipeline that eliminates the need for expert-annotated training data. To optimize the agent's iterative refinement capability, we also introduce Turn-Level GRPO (TL-GRPO), a lightweight, tool-integrated reinforcement learning algorithm that performs turn-level group sampling for fine-grained policy updates. Evaluated on 12 professional analog circuit tasks, SAAC trained with TL-GRPO achieves the best overall performance among the evaluated methods, outperforming Bayesian Optimization and other RL baselines. Moreover, SAAC demonstrates generalization to unseen circuit specifications, providing a practical foundation for LLM-driven automation in electronic design.