Paretorouter: VLSI Global Routing With Multi-Objective Optimization

Global routing (GR) has been a central task in modern chip design. Many efforts, either ML-based or heuristic, have been proposed that seek to optimize specific business goals, such as overflow (OF) and wirelength (WL) of generated routes. Notably, recent end-to-end neural routers have demonstrated significant speed advantages in optimizing wirelength, yet they struggle to achieve efficiency in reducing overflow. In fact, a good trade-off between the above two metrics has not been achieved, especially when overall efficiency is pursued, as existing ML-based methods often optimize only a single metric. To bridge this gap for more practical industry applications, we propose a flow-matching-based router for GR, called ParetoRouter, which achieves trade-offs between WL and OF, generating highly connected routes at high speed and quality. In the training phase, two differential metric-oriented routing results are utilized to build the training datasets. Beyond their average—a base 'Average Flow' between pins and routes—we introduce a disambiguation objective that mitigates discrete topological artifacts. A Pareto sampling method, based on the Das-Dennis method, is also devised to achieve trade-offs between OF and WL in the inference phase. Extensive experimental results show that it achieves the lowest (or tied-lowest) **overflow** on all evaluated benchmarks and, compared with the end-to-end DSBRouter, produces **fewer superfluous routes** on ISPD07 with **over 70x** less generation time.