Chip Protection Area Design: Dataset and Evaluation

The protection area surrounding a semiconductor chip guards its circuit against thermo-mechanical defects induced during wafer dicing. Its 2D designs are governed by manufacturing constraints and evaluated using test chips that require production processes with substantial costs. An ideal design should achieve optimal 3D mechanical states while meeting the hard constraints. This creates a highly nonlinear optimization landscape where data-driven approaches had show strong promise in other domains. Given the lack of large-scale semiconductor protection area datasets with 3D thermo-mechanical elasto-plastic evaluation, we propose the first 1.17 TB public dataset, containing 110,170 protection area layouts across 18 metal stacks, each paired with fields from thermo-mechanical elasto-plastic finite element simulations. We demonstrate that the dataset enables two key benchmarks: design-to-fields cross-dimensional forward prediction, and fields-to-design inverse generation. The baseline results establish the difficulty of these tasks and highlight opportunities for data-driven methods to address industrial design bottlenecks. In addition to the dataset, we provide an open-source end-to-end automated pipeline from design generation to simulation for reproducibility and potential extensions.