LASSO: Learning Agentic Self-Synthesized Oracles for Golden-Free RTL Generation

Agentic RTL generation succeeds when a trusted testbench supplies feedback, but a specification-to-silicon flow rarely starts with one: the agent must construct its own verifier, and a lenient verifier silently approves incorrect hardware. We argue that learning in this setting should follow the structure of hardware verification. We first introduce LASSO, a golden-free agentic flow whose stages are inspired by formal-verification practice: specification-linked conditions, reconciliation of independently generated reference models through minimized distinguishing traces, vacuity checks, mutation-based adequacy qualification, and counterexample triage that separates design faults from verifier faults. With the same DeepSeek V4 backbone, LASSO improves pass@1 over direct generation and over the golden-free ChipMATE flow on all four benchmarks we evaluate; with Qwen3.8-27B on VerilogEval-v2, it closes most of the gap to golden-testbench feedback. A final-outcome reward does not directly evaluate verifier quality: when the final design is faulty, a verifier that falsely accepts it receives the same credit as one that correctly rejects it. On held-out CVDP bug-fix tasks, outcome-reward training does not improve Qwen3.8-27B (62.9% vs. 65.7% pass@1). We therefore propose VCPO, in which each artifact of the flow is learned against its own verification contract—soundness and adequacy for the verifier, correct, evidence-backed verdicts for diagnosis, and counterexample elimination for the design—and compared only with alternatives for the same artifact on the same specification. On the same tasks, VCPO raises pass@1 to 71.4%, closing 40% of the gap to golden-testbench feedback, and cuts the false self-acceptance rate from 14.3% to 5.7%.