VeriRefine: An LLM-Enabled Abstraction Refinement Flow for RTL Design Generation

Large language models (LLMs) can generate register-transfer-level (RTL) designs from natural-language specifications, yet many generation errors stem from misinterpreting the specification. Intermediate representations make specification interpretations explicit, but these interpretations still require checks for missing requirements and contradictions with the source specification. This paper presents VeriRefine, an LLM-enabled abstraction-refinement framework that refines informal specifications into schema-constrained Abstract Signal Transition Functions (ASTFs), capturing per-signal logic, clocking, reset, and transition semantics before RTL generation. The resulting ASTF-based representation is audited for specification grounding, coverage, consistency, state transition integrity, and RTL design-rule compliance. Post-generation simulation failures are classified to guide ASTF refinement or RTL repair. Using Claude Sonnet 4.6, VeriRefine achieves 96.0% functional correctness on RTLLM v2.0 and 98.1% on VerilogEval-Human v2, exceeding direct generation by 32.0 and 12.8 percentage points, respectively. Iterative debugging improves upon the audited generation flow on benchmarks.