TA-DMP-SNN: A Topology-Aware Dual-Memory Pareto Spiking Neural Search Network for Multiobjective Reed-Muller Logic Synthesis

The ternary polarity space of Reed–Muller (RM) logic grows exponentially with the number of variables, while area, power, delay, and reliability objectives often conflict. We propose TA-DMP-SNN, a Topology-Aware Dual-Memory Pareto Spiking Neural Network for multiobjective RM logic synthesis. Unlike approaches that use neural networks only as quality predictors, TA-DMP-SNN directly employs an SNN as a discrete search mechanism over the ternary polarity space. Circuit topology, RM-term co-occurrence, and structural relations are encoded through topology-aware synaptic gating. Reference-vector routing, fast eligibility traces, and slow nondominated-archive memory jointly regulate exploration and consolidation. Across eight nontrivial RM benchmark circuits, TA-DMP-SNN achieved the highest median four-objective hypervolume after 100 unique evaluations, with a median absolute gain of 0.143 and a median improvement of 56.0% over the strongest baseline.