CIRCUIT-R1: CIRCUIT-GROUNDED REINFORCEMENT LEARNING FOR VERIFIABLE CIRCUIT2NETLIST

Recent multimodal large language models have shown strong visual reasoning capabilities, yet reliable circuit-to-netlist translation remains challenging. Exist- ing circuit-oriented reasoning methods use reinforcement learning to reward only a subset of intermediate reasoning stages, leaving the grounding of circuit con- nections insufficiently constrained. We investigate this limitation from two com- plementary perspectives. From an explicit perspective, our analysis shows that recognizing devices and ports alone is insufficient: wire tracing provides essential geometric evidence for recovering circuit topology. From an implicit perspec- tive, generated netlists frequently violate basic structural and electrical principles, demonstrating the need for circuit-specific priors beyond visible image evidence. Motivated by these findings, we introduce CIRCUIT-R1 (Circuit-Grounded Re- inforcement Learning for Verifiable Circuit-to-Netlist Translation) . CIRCUIT-R1 decomposes netlist generation into five reasoning stages and defines continuous reward signals over bounding boxes, terminal centers, wire polylines, and end- point assignments. We further propose the Circuit Physics Prior Verifier (CPPV), which represents each predicted netlist as a typed terminal hypergraph and detects structural and electrical violations without consulting the ground-truth netlist. We will release Cir-GCoT, a dataset of 2,440 circuit schematics with fine-grained grounding and topology annotations. Our results show that explicit visual evi- dence and implicit circuit priors jointly guide policy optimization toward accurate and reliable netlist generation.