SLIC: Reinforcement Fine-Tuning Small LMs for Multi-Turn Analog Circuit Optimization

Analog integrated circuit (IC) design is a multi-turn, simulator-grounded engineering task that demands iterative reasoning over coupled performance trade-offs, yet proprietary process design kits (PDKs) make hosted large-language-model workflows difficult to deploy in practical design settings. We present SLIC — Small LM Iterating on Circuits — a reinforcement fine-tuning framework that trains a 7B-scale, locally deployable language model for closed-loop analog circuit optimization. SLIC pairs structured circuit representations with discretized relative-update actions, domain- and difficulty-gated multi-objective rewards, and Reward-Guided Rollout Steering (RGRS), which turns per-step simulator feedback into both policy-learning and trajectory-steering signals in this sparse, highly constrained domain. We further release an open, goal-conditioned benchmark of 34 amplifier topologies with standardized protocols for in-distribution validation, held-out topology evaluation, and cross-technology-node transfer. Trained solely on a 22 nm silicon CMOS PDK, SLIC achieves 58.7% in-distribution Pass@1 under a 4-turn simulator budget, surpassing the 1.6T DeepSeek-V4-Pro Think baseline by 12.7 percentage points. Beyond the training distribution, it reaches 51.5% Pass@1 on held-out topologies, improving over the same baseline by 10.6 percentage points, and consistently transfers across five unseen technology nodes (32–130 nm) without additional fine-tuning. Performance further scales with test-time simulator interactions, reaching roughly 70% Pass@1 at an 8-turn budget, demonstrating that SLIC enables the small policy to convert additional simulator calls into improved circuit designs.