PV-Debugger: Agentic Debugging for VLSI Physical Verification

Electronic design automation (EDA) has automated much of the very large-scale integrated circuit (VLSI) design flow, yet physical verification (PV) remains manual. Debugging design rule checking (DRC) violations and layout-versus-schematic (LVS) mismatches in PV requires interpreting reports, localizing faults, repairing layouts, and iteratively re-running sign-off, a challenging workflow largely unexplored by existing agents. We present PV-Debugger, a framework for agentic PV debugging with three components: PV-Bench, 99 DRC and LVS debugging tasks across 5 real designs; PV-World, a reproducible GUI-based environment built entirely on the benchmark, open-source semiconductor technologies, and EDA tools; and PV-Agent, an expert-aligned multi-agent framework that grounds diagnosis and repair in design rules, layout geometry, and sign-off feedback. Experiments show that general-purpose agents struggle on PV-Bench in PV-World, with the strongest baseline solving only 23.2% of tasks. PV-Agent raises the pass rate to 54.5% on the same backbone and improves LVS debugging from 11.1% to 44.4%. PV-Debugger establishes PV as a challenging, automatically verifiable testbed for multimodal, tool-using agents and offers a foundation for developing specialized agents for real-world chip-design workflows.