PEACache: Progressive Error Alignment for Diffusion Transformer Caching

Diffusion Transformers (DiTs) exhibit strong generative capabilities but require repeated and computationally expensive denoiser evaluations. Feature caching reduces this cost by reusing intermediate computations, but inevitably introduces reuse-induced errors. In this work, we propose PEACache, a Progressive Error Alignment framework that controls caching errors at three progressively higher levels. At the branch level, instead of modeling the Transformer residual at a cached step as in most existing methods, we directly model the error caused by residual reuse, i.e., the missing residual change. Through SVD analysis, we show that this error can be more effectively corrected using historical residual changes, motivating a historical residual change subspace with adaptive spectral rank and update magnitude. At the classifier-free guidance (CFG) level, we show that independently optimizing branch-level errors can still lead to larger CFG output errors, since CFG combines conditional and unconditional predictions and its guidance scale amplifies their mismatch. We therefore supervise cache prediction directly on the CFG-composed output. At the final-latent level, we estimate the impact of caching each individual step on the final latent and use their accumulated impact as a scheduling surrogate, which is optimized via dynamic programming under a computation budget. On Wan2.1-1.3B, Open-Sora 1.2, and CogVideoX, our method substantially improves output fidelity at comparable acceleration. On Wan2.1-1.3B, among compared methods achieving over $3\times$ acceleration, Progressive Error Alignment improves the previous best SSIM/PSNR/LPIPS from $0.629/17.160/0.290$ to $0.730/21.543/0.188$.