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Under review as a conference paper at ICLR 2027

The Hidden Signal of Verifier Strictness: Controlling and Improving Step-Wise Verification via Selective Latent Steering

Abstract

Generative verifiers have emerged as a promising paradigm for step-wise verification, but their verification behavior is often poorly calibrated: they may be under-critical and miss erroneous steps, or over-critical and reject correct reasoning. We refer to the verifier's tendency toward stricter or more lenient judgments as verifier strictness. We identify hidden-state directions at verification-paragraph boundaries that modulate verifier strictness without fine-tuning the verifier. However, uniform steering induces a trade-off between error detection and correctness certification. To address this, we propose VerifySteer, which exploits latent correctness signals for sample-level routing and selectively intervenes on paragraph boundaries. Experiments on ProcessBench and Hard2Verify show that VerifySteer outperforms prompt optimization and activation steering baselines, and is competitive with self-consistency while requiring - less inference compute. VerifySteer is also complementary to verification fine-tuning, providing further gains on top of fine-tuned verifiers.

open until 14 Dec 2026

est. 32% chance this paper gets accepted at ICLR 2027.

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