RVVCoder: ISA-Grounded LLMs for High-Performance RISC-V Vector Kernel Generation

Open RISC-V hardware is spreading rapidly, yet every new vector core needs efficient kernels, and hand-writing RISC-V Vector (Rvv) assembly is costly. Rvv is vector-length agnostic, so a kernel must stay correct across vector lengths and fast on each core, which challenges both compilers and large language models (LLMs). We formalize Rvv kernel generation under instruction-set architecture (ISA) and hardware constraints and propose RvvCoder. RvvBench pairs RvvCoT, a specification-guided corpus, with a 38-operator suite verified across vector lengths and timed on real boards. RvvCoder learns ISA rules by supervised fine-tuning, then improves by reinforcement learning on kernels executed in QEMU and on hardware, where Decomposed Execution Verification (DEV) rewards partial progress. RvvCoder reaches 59% ER@10 correctness versus 13% for GPT-5.5, and its verified kernels run up to $1.49\times$ faster than the strongest applicable baselines on two Rvv boards, confirming the value of hardware feedback.