FabBench: A Fabrication-Informed Benchmark for SEM-Domain Process-Conditioned Lithography Models

Accurately predicting semiconductor lithography patterns and defect states under continuous process parameters is vital for advanced chip design. However, existing benchmarks either focus purely on physics simulation or isolate defect analysis from SEM domain observations. The scarcity of process-annotated wafer data further prevents joint evaluation of geometric evolution and defect formation under continuous process variations, leaving their coupled behavior largely unexamined. Moreover, conventional image-level metrics are poorly aligned with fabrication-side assessment, often obscuring localized metrological errors and failures in defect prediction. To address these limitations, we introduce **FabBench**, the first comprehensive benchmark for evaluating process-conditioned geometric evolution and defect formation in the SEM domain. Built on 547K physics-grounded, real-SEM-informed triplets with structured in-distribution and out-of-distribution splits, FabBench establishes a hierarchical, metrology-aware evaluation protocol spanning visual fidelity, localized dimensional accuracy, and topological defect consistency. Extensive evaluations show that predictions with high image-level similarity can still exhibit substantial errors under fabrication-aligned metrology and defect metrics, revealing a critical gap between visual fidelity and fabrication-relevant accuracy. FabBench thus provides a unified testbed for developing models that accurately capture both fine-grained geometric responses and topological defect formation across continuous process variations.